Paper Title: Linear Ramp Generator for ADC BIST

Author's name: M Senthilsivakumar

Paper abstract: This paper presents a design of linear ramp generator for on-chip testing of analog to digital converter. Linear ramp signal is generated by the design of MOS transistor logic based ramp generator and applied to the converter for extending the test accuracy. The primary non-idealities affecting the linearity and timing of the ramp generator are discussed and overcome in this work. A comparator based feedback configuration is used to maintain the linearity and eliminate the offset in ramp voltage position and transient time, which are insistent requirements in on-chip analog and mixed-signal IC testing. The proposed linear ramp generator is implemented in 0.18μm CMOS technology, and the simulation results are observed to exhibit the performance and feasibility in analog to digital converter testing. The observed results show that the proposed ramp generator achieves oscillation frequency of 5 MHz with the power consumption of 113.74μW from 2V supply voltage. The effective layout area of ramp generator is 45.9μm˟18.9μm.

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